Semiconductor Engineering

Package Assembly Design Kits: The Future Of Advanced Package Design

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized ...
Hackaday

Working With BGAs: Design And Layout

The Ball Grid Array, or BGA package is no longer the exclusive preserve of large, complex chips on computer motherboards: today even simple microcontrollers are available with those little solder ...
Yahoo

Cadence SiP Technologies and Allegro Package Designer Optimized for Hand-Held Consumer Electronics Market

TEMPE, AZ--(Marketwire - Oct 22, 2012) - EPEPS -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced enhancements to its Allegro ® 16.6 ...
Business Insider

AnaGlobe Technology Will Introduce a Unified Chip-Package Layout Solution at the TSMC 2017 OIP Ecosystem Forum

SANTA CLARA, Calif., Sept. 5, 2017 /PRNewswire/ -- AnaGlobe Technology, Inc., a leader in layout integration solutions, will announce a unified chip-package layout solution, with features and extended ...
Design-Reuse

SoC package design takes 'bottom-up' tack

As system-on-chip designs migrate to nanometer silicon, packaging technology is challenged to keep pace with the integration and performance capabilities offered. Nowhere is this more so than in ...
EDN

Flip-chip designs need efficient methodology

With process nodes and die sizes shrinking, the number of consumer products incorporating ICs with flip-chip packaging is growing. Unfortunately, flip-chip package manufacturing rules have not kept ...
Design-Reuse

Design optimization of flip-chip packages integrating USB 3.0

As the speeds of various SerDes interfaces move into the multi-gigabits/sec range, more ASIC chips are being designed to have multiple high speed interfaces such as USB 3.0, PCIE Gen3, DDR3, and ...
Semiconductor Engineering

High Performance, Multi-Chip Leadframe Package With Internal Connections

For high performance applications, demand for highly integrated packages has increased. This is due to the highly integrated package’s electrical performance advantages of reduction of interchip ...
Electronic Design

Floorplanning A Power Delivery Network With Spice

Greater system complexity and ever-higher clock speeds continue to push IC power consumption to the limit. And though every generation escalates the demand on IC current, voltage levels drop due to ...
Electronic Design

Motor-Driver PCB Layout Guidelines (Part 2)

6. SOT-23 and SOIC packages are typically used in low-power motor drivers. Standard leaded packages, like SOIC and SOT-23 packages, are often used for low-power motor drivers (Fig. 6). To maximize the ...
EDN

Chip-and-package co-design relieves pressure on complex designs

The vise is closing down on design departments.Manufacturers want more capabilitiesin their products than ever before. It’simperative for manufacturers to remaincompetitive. Marketing, meanwhile,wants ...