Design-Reuse

FPGA based Complex System Designs: Methodology and Techniques

Today platform-FPGAs are fabricated in nanometer technologies with multi-million gate densities; hard/soft macros such as embedded processors, RAMs, multipliers, DSP blocks, analog cells and high ...
EDN

Book Excerpt: FPGA-based Prototyping Methodology Manual

This book collects the best practices FPGA-based Prototyping of SoC and ASIC devices into one place for the first time, drawing upon not only the authors' own knowledge but also from leading ...
Design-Reuse

FPGA Prototyping as a Verification Methodology

To some degree, FPGA prototyping has become commonplace in the majority of SoC development programs. This paper is a brief discussion of four aspects of this type of approach. First the forces behind ...
Yahoo Finance

BaySand Introduces Enhanced FPGA to ASIC Conversion Program With IP Partners and Supporting Tools

Metal Copy-28 Matches 28nm FPGA Capabilities, While Significantly Reducing Power Consumption and at a Fraction of the FPGA Unit Price Metal Copy is a low risk and efficient FPGA to ASIC conversion.
Electronic Design

FPGA Q&A: Lattice Semiconductor

Electronic Design held a series of Q&A sessions with several major FPGA companies. Here, our roundtable discussion with Lattice Semiconductor included Bertrand Leigh, director of applications ...
New Electronics

Faster FPGA verification

Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry. Today, design verification accounts for more than ...
Electronics Weekly

Thales links with Mentor Graphics for FPGA design training

Thales has worked with design tool firm Mentor Graphics to develop a new type of tool and design methodology training course which the defence firm will offer to a hundred engineers over the coming ...
Electronic Design

ASIC-Like FPGA Methodology Saves Up To $9,925,000 In NRE Costs

Not all companies have $10 million in their back pockets for the non-recurring expenses (NRE) today's ASIC design starts require. Fortunately, that kind of cash isn't necessary anymore, thanks to ...
Yahoo Finance

MicroCloud Hologram Inc. Proposes Quantum AI Simulator Adopting Hybrid CPU-FPGA Method, Achieving Efficient Image Classification Simulation Through Heterogeneous Computing

SHENZHEN, China, Feb. 26, 2026 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, proposed a quantum AI simulator that adopts a ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

Book Review: FPGA-Based Prototyping Methodology Manual

Synopsys, in cooperation with Xilinx, ARM, LSI and nVidia, has just released a new book on the subject of FPGA-Based prototyping – one of my favorite subjects (Click Here to visit the appropriate ...