Nanowerk

Novel dual-gate transistor design enables stable 3D semiconductor stacking

Researchers developed a dual-modulated vertically stacked transistor that eliminates current leakage at nanoscale channel ...
Electronic Design

Dual Transistors Bask Together In Close Quarters

Taking up less space than similar SOT-23 devices, the low-noise, high-gain CMKT5078, CMKT5087 and CMKT5088 dual transistors come housed in a SOT-363 surface-mount package having a nominal profile of 0 ...
Nanowerk

Dual-gate vertical transistor enables stable nanoscale 3D chip stacking

Researchers developed a dual-modulated vertical transistor that suppresses leakage at nanoscale channels and supports ...
Tech Xplore on MSN

Key transistor for next-generation 3D stacked semiconductors operates without current leakage

A research team led by Professor Jae Eun Jang and Dr. Goeun Pyo from the Department of Electrical Engineering and Computer ...
Electronic Design

Dual Transistor Eases VCO Design

The UPA895TD twin transistor combines two NE851 NPN oscillator chips in a six-pin TD package measuring 1.2 mm x 0.8 mm. In essence, users can design two voltage-controlled oscillators (VCOs) with a ...
Semiconductor Engineering

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)

An ultra-scaled memory device, called `Dynamic Flash Memory (DFM)’. With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F 2 cell can be achieved. “This paper proposes an ultra-scaled ...