Semiconductor Engineering

Transistor-Level Verification Returns

Technologies that had become specialist tools are moving back into mainstream usage; shift left is not just about doing things earlier in the flow. A few decades ago, all designers did ...
Design-Reuse

Cadence Introduces Voltus-Fi Custom Power Integrity Solution, Delivering Foundry-Certified SPICE-Level Accuracy for Transistor-Level Power Signoff

SAN JOSE, Calif. -- Aug 4, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced Cadence® Voltus™-Fi Custom Power Integrity Solution, a ...
Business Wire

Pulsic at DAC 2016: Overcoming the Traditional Bottlenecks in Transistor-Level and Cell-Level Custom Design Flows

SAN JOSE, Calif.--(BUSINESS WIRE)--Typically, there are three phases in custom design flows where time to final layout has been a bottleneck: area estimation, layout / simulation cycle and final ...
Semiconductor Engineering

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual ...
EDN

Cadence Introduces Voltus-Fi Custom Power Integrity Solution, Delivering Foundry-Certified SPICE-Level Accuracy for Transistor-Level Power Signoff

Voltus-Fi Custom Power Integrity Solution enables designers to shrink the critical power signoff closure and analysis phase through key capabilities including: Cadence's patented voltage-based ...