TOKYO — Swiss-based Innovative Silicon Solutions (ISS) and the Swiss Federal Institute of Technology have developed a silicon-on-insulator based single-transistor DRAM cell prototype that will scale ...

As mentioned in a previous post, the Flemish Interuniversity Microelectronics Consortium, IMEC, has decided to include the interests of DRAM and non-volatile memory designers in their 32nm half-pitch ...

NEO Semiconductor has announced that it has developed the "world's first 3D NAND-like DRAM cell array," which aims to increase DRAM chip density using established 3D stacking technology. Designed to ...

NEO Semiconductor has unveiled its "3D X-DRAM", which it is pitching as the world's first 3D NAND-like DRAM cell array. Based on Neo's estimates, 3D X-DRAM technology can achieve 128 Gb density with ...

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...

One-transistor, one-capacitor (1T-1C) DRAM cells have been commercially implemented since at least 1999. They save die area compared to conventional 6-T DRAM cells, use less power, yield better, and ...

This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access ...

NEO's IGZO-based 3D X-DRAM delivers up to 512Gb density and 450-second retention with ultra-low power consumption — built on 3D NAND-compatible processes and optimized for AI, in-memory computing, and ...

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, ...