EDN

Power management can cause latchup in CMOS chips

If you leave signals applied to the inputs of a CMOS chip with the power turned off, the chip might explode when you re-apply power. This is called latchup. Similarly, if you drag the outputs of a ...
EDN

Novel low-power high-gain CMOS LNA for UWB receivers

Abstract: This paper presents a highly linear low power and high gain CMOS common-gate (CG) LNA for UWB receivers. The proposed LNA uses current-reuse, forward-body biasing, and shunt-series peaking ...
Nature

CMOS Technology for Neural Stimulation and Power Management

CMOS technology has become a fundamental enabler in the advancement of neural stimulation devices, combining the benefits of low-power operation with high-density integration, thus allowing for ...
Electronic Design

Low Power, High Performance CMOS Logic

Scientists at the Tokyo Institute of Technology have developed low power, high performance CMOS logic technology that is vital to the future of microprocessors and system-on-chip (SoC) devices for ...
Electronic Design

AdaptiveRF CMOS Transmit Modules Conserve Cell-Phone Power

Employing a standard CMOS process, Amalfi Semiconductor’s family of dual- and quad-band transmit modules offer lower current consumption for applications such as front-end GSM/GPRS cellular handsets.
AFP

Toshiba Releases High-Speed Response, Full Input/Output Range CMOS Dual Comparator Suitable for Overcurrent Detection in Industrial Equipment

Toshiba Electronic Devices & Storage Corporation ("Toshiba") has launched a CMOS dual comparator, "TC75W71FU." It features a high-speed response and a full input/output range (Rail to Rail), suiting ...