Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as ...

Design of power/driver ICs in compliance with latchup qualification requirements involves a conceptually different approach in comparison with digital LV (low voltage) ICs. The LV ICs’ electrostatic ...

In VLSI layout design, density issues are critical factors influencing the performance, yield, and reliability of integrated circuits. This whitepaper delves into the several types of density issues, ...

The design teams typically invest years and numerous iterations to validate IP and produce a functioning chip. Once this validation is complete, they create derivatives of the silicon-proven IP, often ...